1. Field of the Invention
The present invention is related to a gate driver, and more particularly, to a gate driver with an output enable control circuit.
2. Description of the Prior Art
Please refer to FIG. 1. FIG. 1 is a diagram illustrating the gate driver 10 of a conventional Liquid Crystal Display (LCD) device. The gate driver includes a shift register 101, a logic control circuit 102, and an output driving circuit 103. The shift register 101 generates the scan signals X1˜Xm according to the vertical synchronous signal STV and the vertical clock signal CPV, and transmits the vertical synchronous signal STV to a next gate driver 10. The logic control circuit 102 is electrically connected to the shift register 101 and the logic control circuit 102 outputs the scan signals X1˜Xm according to the output enable signal OE. The output driving circuit 103 is electrically connected to the logic control circuit 102. The output driving circuit 103 converts the voltage level of the scan signals X1˜Xm for generating the gate signals G1˜Gm according to the gate high voltage VGH and the gate low voltage level VGL. The vertical synchronous signal STV, the vertical clock signal CPV and the output enable signal OE are provide by a timing controller 12.
Please refer to FIG. 2. FIG. 2 is a waveform diagram illustrating the signals provided by the timing controller 12. The gate driver 10 generates the gate signals G1˜Gm according to the vertical synchronous signal STV, the vertical clock signal CPV and the output enable signal OE provided from the timing controller 12. When the output enable signal OE is at a low voltage level, the logic control circuit 102 outputs the scan signals X1˜Xm and when the output enable signal OE is at a high voltage level, the logic control circuit 102 stops outputting the scan signals X1˜Xm. Generally the logic control circuit 102 utilizes the output enable signal OE to block the scan signals X1˜Xm being outputted within the period of the first frame. Meanwhile, the logic control circuit 102 performs, in coordination with the vertical synchronous signal STV and the vertical clock signal CPV (i.e. this is when the vertical synchronous signal STV and the vertical clock signal CPV are both at a high voltage level at the same time), a logic reset to the gate driver 10 for preventing the occurrence of excessive current in which the gate driver 10 is likely to be damaged. During the logic reset, it is necessary for the output enable signal OE to be maintained at a high voltage level until the vertical synchronous signal STV and the vertical clock signal CPV are both triggered (i.e. at a high voltage level) together for two times.
Please refer to FIG. 3. FIG. 3 is a waveform diagram illustrating the delay of the vertical clock signal CPV. When the output of the vertical clock signal CPV is delayed, the logic reset of the gate driver 10 is unable to be completed within the period of the first frame. However, in the subsequent frame (i.e. the second frame) the enable signal OE is converted from the high voltage level to the low voltage level, for outputting the scan signals X1˜Xm. Therefore, the logic reset of the gate driver 10 is incomplete and consequently excessive current may be generated and the gate driver 10 is likely to be damaged.
Please refer to FIG. 4. FIG. 4 is a waveform diagram illustrating the delay of the output enable signal OE. Since the output of the scan signals X1˜Xm is blocked only when the output enable signal OE is at a high voltage level, so when the output of the output enable signal OE is delayed, the gate driver 10 is likely to output the scan signals X1˜Xm in the period of the first frame. However, the logic reset of the gate driver 10 is performed in the period of the first frame and if the scan signals X1˜Xm are outputted concurrently when the logic reset is incomplete, excessive current may be generated and consequently the gate driver 10 is likely to be damaged.
Therefore, the logic reset of the gate driver 10 is performed prior the gate driver 10 generates the gate signals G1˜Gm; in other words, the vertical synchronous signal STV and the vertical clock signal CPV are both triggered together for two times (i.e. at a high voltage level) and the output enable signal OE is at a high voltage level within the period between the first time and the second time the vertical synchronous signal STV and the vertical clock signal CPV are both triggered, for blocking the scan signals X1˜Xm from being outputted. The delay of the output of the vertical synchronous signal STV or the output enable signal OE causes incomplete logic reset of the gate driver 10. When the logic reset of the gate driver 10 is incomplete, excessive current may be generated and consequently the gate driver 10 is likely to be damaged.